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19-1476; Rev 0; 4/99
Low-Power, Serial, 14-Bit DACs with Force/Sense Voltage Output
General Description
The MAX5171/MAX5173 low-power, serial, voltage-output, 14-bit digital-to-analog converters (DACs) feature a precision output amplifier in a space-saving 16-pin QSOP package. The MAX5171 operates from a +5V single supply, and the MAX5173 operates from a +3V single supply. The output amplifier's inverting input is available to allow specific gain configurations, remote sensing, and high output current capability. This makes the MAX5171/ MAX5173 ideal for a wide range of applications, including industrial process control. Both devices draw only 260A of supply current, which reduces to 1A in shutdown mode. In addition, the programmable power-up reset feature allows for a user-selectable output voltage of either 0 or midscale. The 3-wire serial interface is compatible with SPITM, QSPITM, and MICROWIRETM standards. An input register followed by a DAC register provides a double-buffered input, allowing the input and DAC registers to be updated independently or simultaneously with a 16-bit serial word. Additional features include software and hardware shutdown, shutdown lockout, a hardware clear pin, and a reference input capable of accepting DC and offset AC signals. These devices provide a programmable digital output pin for added functionality and a serial-data output pin for daisy-chaining. All logic inputs are TTL/CMOScompatible and are internally buffered with Schmitt triggers to allow direct interfacing to optocouplers. The MAX5171/MAX5173 incorporate a proprietary on-chip circuit that keeps the output voltage virtually "glitch free," limiting the glitches to a few millivolts during power-up. Both devices are available in 16-pin QSOP packages and are specified for the extended (-40C to +85C) temperature range. The MAX5171/MAX5173 are pin-compatible upgrades to the 12-bit MAX5175/MAX5177. For 100% pincompatible DACs with an internal reference, see the 13-bit MAX5132/MAX5133 and the 12-bit MAX5122/MAX5123 data sheets. o 1 LSB INL o 1A Shutdown Current o "Glitch Free" Output Voltage at Power-Up o Single-Supply Operation: +5V (MAX5171) +3V (MAX5173) o Full-Scale Output Range: +2.048V (MAX5173, VREF = +1.25V) +4.096V (MAX5171, VREF = +2.5V ) o Rail-to-Rail(R) Output Amplifier o Low THD (-80dB) in Multiplying Operation o SPI/QSPI/MICROWIRE-Compatible 3-Wire Serial Interface o Programmable Shutdown Mode and Power-Up Reset o Buffered Output Capable of Driving 5k || 100pF Loads o User-Programmable Digital Output Pin Allows Serial Control of External Components o Pin-Compatible Upgrade to the 12-Bit MAX5175/MAX5177
Features
MAX5171/MAX5173
Ordering Information
PART MAX5171AEEE MAX5171BEEE MAX5173AEEE MAX5173BEEE TEMP. RANGE -40C to +85C -40C to +85C -40C to +85C -40C to +85C PIN-PACKAGE 16 QSOP 16 QSOP 16 QSOP 16 QSOP INL (LSB) 1 2 2 4
Pin Configuration
TOP VIEW
FB 1 OUT 2 RS 3 PDL 4 CLR 5 CS 6 DIN 7 SCLK 8 16 VDD 15 N.C. 14 REF
Applications
Digitally Programmable 4-20mA Current Loops Industrial Process Control Digital Offset and Gain Adjustment Motion Control Automatic Test Equipment (ATE) Remote Industrial Controls P-Controlled Systems
SPI and QSPI are trademarks of Motorola, Inc. MICROWIRE is a trademark of National Semiconductor Corp. Rail-to-Rail is a registered trademark of Nippon Motorola, Ltd.
MAX5171 MAX5173
13 AGND 12 SHDN 11 UPO 10 DOUT 9 DGND
QSOP
Functional Diagram appears at end of data sheet.
1
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Low-Power, Serial, 14-Bit DACs with Force/Sense Voltage Output MAX5171/MAX5173
ABSOLUTE MAXIMUM RATINGS
VDD to AGND, DGND ............................................-0.3V to +6.0V AGND to DGND.....................................................-0.3V to +0.3V Digital Inputs to DGND..........................................-0.3V to +6.0V DOUT, UPO to DGND ................................-0.3V to (VDD + 0.3V) FB, OUT, REF to AGND .............................-0.3V to (VDD + 0.3V) Maximum Current into Any Pin............................................50mA Continuous Power Dissipation (TA = +70C) 16-pin QSOP (derate 8mW/C above +70C)..............667mW Operating Temperature Range ...........................-40C to +85C Storage Temperature Range .............................-65C to +150C Lead Temperature (soldering, 10sec) .............................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS--MAX5171
(VDD = +5.0V 10%, VREF = +2.5V, AGND = DGND, FB = OUT, RL = 5k, CL = 100pF referenced to ground, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) PARAMETER STATIC PERFORMANCE Resolution Integral Nonlinearity (Note 1) Differential Nonlinearity Offset Error (Note 2) Gain Error Power-Supply Rejection Ratio Output Noise Voltage Output Thermal Noise Density REFERENCE Reference Input Range Reference Input Resistance Reference -3dB Bandwidth Reference Feedthrough Signal-to-Noise Plus Distortion Ratio DIGITAL INPUTS Input High Voltage Input Low Voltage Input Hysteresis Input Leakage Current Input Capacitance DIGITAL OUTPUTS Output High Voltage Output Low Voltage VOH VOL ISOURCE = 2mA ISINK = 2mA VDD - 0.5 0.13 0.4 V V SINAD VREF RREF VREF = 0.5Vp-p + 2.5VDC, slew-rate limited VREF = 3.6Vp-p + 1.8VDC, f = 1kHz, code = all 0s VREF = 1.4Vp-p + 2.5VDC, f = 10kHz, code = 3FFF hex 3 0.8 200 VIN = 0 or VDD 0.001 8 1 0 18 350 -84 84 VDD - 1.4 V k kHz dB dB INL DNL VOS GE PSRR f = 100kHz RL = RL = 5k -0.6 -1.6 10 1 50 MAX5171A MAX5171B 14 1 2 1 10 4 8 120 Bits LSB LSB mV LSB V/V LSBp-p nV/Hz SYMBOL CONDITIONS MIN TYP MAX UNITS
MULTIPLYING-MODE PERFORMANCE
VIH VIL VHYS IIN CIN
V V mV A pF
2
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Low-Power, Serial, 14-Bit DACs with Force/Sense Voltage Output
ELECTRICAL CHARACTERISTICS--MAX5171 (continued)
(VDD = +5V 10%, VREF = +2.5V, AGND = DGND, FB = OUT, RL = 5k, CL = 100pF referenced to ground, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) PARAMETER DYNAMIC PERFORMANCE Voltage Output Slew Rate Output Settling Time Output Voltage Swing (Note 3) Current into FB Time Required to Exit Shutdown Digital Feedthrough POWER SUPPLIES Positive Supply Voltage Power-Supply Current (Note 4) Shutdown Current (Note 4) TIMING CHARACTERISTICS SCLK Clock Period SCLK Pulse Width High SCLK Pulse Width Low CS Fall to SCLK Rise Setup Time SCLK Rise to CS Rise Hold Time SDI Setup Time SDI Hold Time SCLK Rise to DOUT Valid Propagation Delay SCLK Fall to DOUT Valid Propagation Delay SCLK Rise to CS Fall Delay CS Rise to SCLK Rise Hold Time CS Pulse Width High tCP tCH tCL tCSS tCSH tDS tDH tDO1 tDO2 tCS0 tCS1 tCSW CLOAD = 200pF CLOAD = 200pF 10 40 100 100 40 40 40 0 40 0 80 80 ns ns ns ns ns ns ns ns ns ns ns ns VDD IDD 4.5 0.26 1 5.5 0.35 10 V mA A CS = VDD; fSCLK = 100kHz, VSCLK = 5Vp-p SR To 0.5LSB, from 10mV to full scale 0 -0.1 0 40 1 0.6 12 VDD 0.1 V/s s V A s nV-s SYMBOL CONDITIONS MIN TYP MAX UNITS
MAX5171/MAX5173
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Low-Power, Serial, 14-Bit DACs with Force/Sense Voltage Output MAX5171/MAX5173
ELECTRICAL CHARACTERISTICS--MAX5173
(VDD = +2.7V to +3.6V, VREF = 1.25V, AGND = DGND, FB = OUT, RL = 5k, CL = 100pF referenced to ground, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C). PARAMETER STATIC PERFORMANCE Resolution Integral Nonlinearity (Note 5) Differential Nonlinearity Offset Error (Note 2) Gain Error Power-Supply Rejection Ratio Output Noise Voltage Output Thermal Noise Density REFERENCE Reference Input Range Reference Input Resistance Reference -3dB Bandwidth Reference Feedthrough Signal-to-Noise Plus Distortion Ratio DIGITAL INPUTS Input High Voltage Input Low Voltage Input Hysteresis Input Leakage Current Input Capacitance DIGITAL OUTPUTS Output High Voltage Output Low Voltage VOH VOL ISOURCE = 2mA ISINK = 2mA VDD - 0.5 0.13 0.4 V V VIH VIL VHYS IIN CIN VIN = 0 or VDD -1 200 0.001 8 1 2.2 0.8 V V mV A pF SINAD VREF RREF VREF = 0.5Vp-p + 1.25VDC, slew-rate limited VREF = 1.6Vp-p + 0.8VDC, f = 1kHz, code = all 0s VREF = 0.9Vp-p + 1.25VDC, f = 10kHz, code = 3 FFF Hex 0 18 350 -84 78 VDD - 1.4 V k kHz dB dB INL DNL VOS GE PSRR f = 100kHz RL = RL = 5k -0.6 -1.6 10 2 50 MAX5173A MAX5173B 14 2 4 1 10 4 8 120 Bits LSB LSB mV LSB V/V LSBp-p nV/Hz SYMBOL CONDITIONS MIN TYP MAX UNITS
MULTIPLYING-MODE PERFORMANCE
4
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Low-Power, Serial, 14-Bit DACs with Force/Sense Voltage Output
ELECTRICAL CHARACTERISTICS--MAX5173 (continued)
(VDD = +2.7V to +3.6V, VREF = 1.25V, AGND = DGND, FB = OUT, RL = 5k, CL = 100pF referenced to ground, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C). PARAMETER DYNAMIC PERFORMANCE Voltage Output Slew Rate Output Settling Time Output Voltage Swing (Note 3) Current into FB Time Required to Exit Shutdown Digital Feedthrough POWER SUPPLIES Positive Supply Voltage Power-Supply Current (Note 4) Shutdown Current (Note 4) TIMING CHARACTERISTICS SCLK Clock Period SCLK Pulse Width High SCLK Pulse Width Low CS Fall to SCLK Rise Setup Time SCLK Rise to CS Rise Hold Time SDI Setup Time SDI Hold Time SCLK Rise to DOUT Valid Propagation Delay SCLK Fall to DOUT Valid Propagation Delay SCLK Rise to CS Fall Delay CS Rise to SCLK Rise Hold Time CS Pulse Width High Note 1: Note 2: Note 3: Note 4: Note 5: tCP tCH tCL tCSS tCSS tDS tDH tDO1 tDO2 tCS0 tCS1 tCSW CLOAD = 200pF CLOAD = 200pF 10 75 150 150 75 75 60 0 60 0 200 200 ns ns ns ns ns ns ns ns ns ns ns ns VDD IDD 2.7 0.26 1 3.6 0.35 10 V mA A CS = VDD, DIN = 50kHz; fSCLK = 100kHz, VSCLK = 3Vp-p SR To 0.5LSB, from 10mV to full-scale 0 -0.1 0 40 1 0.6 12 VDD 0.1 V/s s V A s nV-s SYMBOL CONDITIONS MIN TYP MAX UNITS
MAX5171/MAX5173
INL guaranteed between codes 64 and 16383. Offset is measured at the code that comes closest to 10mV. Accuracy is better than 1.0 LSB for VOUT = 10mV to VDD - 180mV. Guaranteed by PSR test on end points. RL = open and digital inputs are either VDD or DGND. INL guaranteed between codes 128 and 16383.
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Low-Power, Serial, 14-Bit DACs with Force/Sense Voltage Output MAX5171/MAX5173
Typical Operating Characteristics
(MAX5171: VDD = +5V, VREF = 2.5V; MAX5173: VDD = +3V, VREF = 1.25V; CL = 100pF, FB = OUT, code = 3FFF hex, TA = +25C, unless otherwise noted.)
MAX5171
NO LOAD SUPPLY CURRENT vs. SUPPLY VOLTAGE
MAX5171 toc01 MAX5171 toc03 MAX5171-02
310 300 NO-LOAD SUPPLY CURRENT (A) 290 280 270 260 250 240 230 220 210 4.4 4.6 4.8 5.0 5.2 SUPPLY VOLTAGE (V) 5.4
NO LOAD SUPPLY CURRENT vs. TEMPERATURE
266 NO-LOAD SUPPLY CURRENT (A) 264 262 260 258 256 254 252 250 5.6 248 -50 -30 -10 10 30 50 70 90 TEMPERATURE (C) 0.8 -50 1.4 SHUTDOWN SUPPLY CURRENT (A) 1.3 1.2 1.1 1.0 0.9
SHUTDOWN SUPPLY CURRENT vs. TEMPERATURE
-30
-10 10 30 50 TEMPERATURE (C)
70
90
OUTPUT VOLTAGE vs. TEMPERATURE
MAX5171-04
OUTPUT VOLTAGE vs. LOAD RESISTANCE
MAX5171-05
DYNAMIC RESPONSE
2.49950
3.0 2.5 OUTPUT VOLTAGE (V) 2.0 1.5
MAX5171-06
2.49946 OUTPUT VOLTAGE (V)
VCS 5V/div
5V 0
2.49942
2.49938
VOUT 1V/div
2.5V
1.0 0.5
10mV 2s/div
2.49934
2.49930 -50
-30
-10 10 30 50 TEMPERATURE (C)
70
90
0
10
100
10k LOAD RESISTANCE ()
1k
100k
DYNAMIC RESPONSE
MAX5171-07
TOTAL HARMONIC DISTORTION PLUS NOISE vs. FREQUENCY
MAX5171-08
REFERENCE FEEDTHROUGH
VREF = 1.8VDC + 3.6Vp-p at f = 1kHz
MAX5171 toc9
-78 5V 0 THD + NOISE (dB) -80 -82 -84 -86 -88 10mV -90 -92 10 100 1k FREQUENCY (Hz) 10k
0 VOUT/VREF 12.5dB/div
VCS 5V/div
2.5V VOUT 1V/div
2s/div
100k
20
FREQUENCY (Hz)
10k
6
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Low-Power, Serial, 14-Bit DACs with Force/Sense Voltage Output
Typical Operating Characteristics (continued)
(MAX5171: VDD = +5V, VREF = 2.5V; MAX5173: VDD = +3V, VREF = 1.25V; CL = 100pF, FB = OUT, code = 3FFF hex, TA = +25C, unless otherwise noted.)
MAX5171/MAX5173
MAX5171
FFT PLOT
MAX5171 toc10
MAJOR-CARRY TRANSITION
MAX5171 toc11
DIGITAL FEEDTHROUGH
MAX5171 toc12
VREF = 2.5VDC + 1.414Vp-p
VCS 2V/div
VOUT 2mV/div VOUT/VREF 12.5dB/div VOUT 100mV/div
VSCLK 5V/div
0
20
FREQUENCY (Hz)
100k
5s/div
AC-COUPLED
400ns/div
REFERENCE VOLTAGE INPUT FREQUENCY RESPONSE
MAX5171-13
START-UP GLITCH
MAX5171 toc14
0
-5 VDD 1V/div GAIN (dB) -10
-15 VOUT 10mV/div AC-COUPLED VREF = 0.67Vp-p + 2.5VDC -25 0 500 1000 1500 2000 FREQUENCY (kHz) 2500 3000 50ms/div
-20
MAX5173
NO-LOAD SUPPLY CURRENT vs. SUPPLY VOLTAGE
MAX5171 toc15
NO-LOAD SUPPLY CURRENT vs. TEMPERATURE
MAX5173-16
SHUTDOWN SUPPLY CURRENT vs. TEMPERATURE
SHUTDOWN SUPPLY CURRENT (A) 0.58 0.56 0.54 0.52 0.50 0.48 0.46 0.44 -50
MAX5173 toc17
280 275 NO-LOAD SUPPLY CURRENT (A) 270 265 260 255 250 245 240 235 230
268 NO-LOAD SUPPLY CURRENT (A) 266 264 262 260 258 256 254 252
0.60
2.5 2.6 2.7 2.8 2.9 3 3.1 3.2 3.3 3.4 3.5 SUPPLY VOLTAGE (V)
-50
-30
-10
10
30
50
70
90
-30
TEMPERATURE (C)
-10 10 30 50 TEMPERATURE (C)
70
90
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Low-Power, Serial, 14-Bit DACs with Force/Sense Voltage Output MAX5171/MAX5173
Typical Operating Characteristics (continued)
(MAX5171: VDD = +5V, VREF = 2.5V; MAX5173: VDD = +3V, VREF = 1.25V; CL = 100pF, FB = OUT, code = 3FFF hex, TA = +25C, unless otherwise noted.)
MAX5173
OUTPUT VOLTAGE vs. TEMPERATURE
MAX5173-18
OUTPUT VOLTAGE vs. LOAD RESISTANCE
MAX5173-19
DYNAMIC RESPONSE
MAX5173-20
1.2498
1.4 1.2 OUTPUT VOLTAGE (V) 1.0 0.8 0.6 0.4 0.2
1.2497 OUTPUT VOLTAGE (V)
VCS 3V/div
3V 0
1.2496
1.2495
1.25V VOUT 500mV/div 10mV 10 100 1k LOAD () 10k 100k 2s/div
1.2494
12493 -50 -30 -10 10 30 50 70 90 TEMPERATURE (C)
0
DYNAMIC RESPONSE
MAX5173-21
TOTAL HARMONIC DISTORTION PLUS NOISE vs. FREQUENCY
MAX5173-22
REFERENCE FEEDTHROUGH
VREF = 0.8VDC =1.6Vp-p at 1kHz
MAX5173 toc23
-72 3V 0 THD + NOISE (dB) -74 -76 -78 -80 -82 -84 10mV -86 -88 10 100 1k FREQUENCY (Hz) 10k
0
VCS 3V/div
1.25V VOUT 500mV/div
VOUT/VREF 12.5dB/div
2s/div
100k
20
FREQUENCY (Hz)
10k
FFT PLOT
MAX5173 toc24
MAJOR-CARRY TRANSITION
MAX5173 toc25
DIGITAL FEEDTHROUGH
MAX5173 toc26
0 VREF = 1.5VDC + 0.848Vp-p, at f = 10kHz
CS 2V/div
SCLK 2V/div
VOUT/VREF 12.5dB/div
OUT 100mV/div
OUT 500V/div
20
FREQUENCY (Hz)
100k AC-COUPLED
5s/div AC-COUPLED
2s/div
8
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Low-Power, Serial, 14-Bit DACs with Force/Sense Voltage Output
Typical Operating Characteristics (continued)
(MAX5171: VDD = +5V, VREF = 2.5V; MAX5173: VDD = +3V, VREF = 1.25V; CL = 100pF, FB = OUT, code = 3FFF hex, TA = +25C, unless otherwise noted.)
MAX5171/MAX5173
REFERENCE VOLTAGE INPUT FREQUENCY RESPONSE
MAX5173-27
START-UP GLITCH
MAX5173 toc28
0
-5.0 VDD (1V/div) GAIN (dB) -10.0
-15.0 VOUT (10mV/div) VREF = 0.67Vp-p + 1.25VDC -25.0 0 500 1000 1500 2000 2500 3000 AC-COUPLED FREQUENCY (kHz) 50ms/div
-20.0
Pin Description
PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 NAME FB OUT RS PDL CLR CS DIN SCLK DGND DOUT UPO SHDN AGND REF N.C. VDD Feedback Input Voltage Output. High impedance in shutdown. Output voltage is limited to VDD. Reset Mode Select (digital input). Connect to VDD to select midscale reset output value. Connect to DGND to select 0 reset output value. Power-Down Lockout (digital input). Connect to VDD to allow shutdown. Connect to DGND to disable shutdown. Clear DAC (digital input). Clears the DAC to its predetermined output state as set by RS. Chip-Select Input (digital input) Serial-Data Input (digital input). Data is clocked in on the rising edge of SCLK. Serial Clock Input (digital input) Digital Ground Serial-Data Output User-Programmable Output. State is set by serial input. Shutdown (digital input). Pulling SHDN high when PDL = VDD places the chip in shutdown mode with a maximum shutdown current 0f 10A. Analog Ground Reference Input. Maximum VREF is VDD - 1.4V. No Connection Positive Supply. Bypass to AGND with a 4.7F capacitor in parallel with a 0.1F capacitor. FUNCTION
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Low-Power, Serial, 14-Bit DACs with Force/Sense Voltage Output MAX5171/MAX5173
Detailed Description
The MAX5171/MAX5173 14-bit, serial, voltage-output DACs operate with a 3-wire serial interface. These devices include a 16-bit shift register and a doublebuffered input composed of an input register and a DAC register (see Functional Diagram). In addition, the negative terminal of the output amplifier is available. The DACs are designed with an inverted R-2R ladder network (Figure 1), which produces a weighted voltage proportional to the reference voltage.
FB
R
R
R
OUT
2R
2R
2R
2R
2R D11
Reference Input
The reference input accepts both AC and DC values with a voltage range extending from 0 to VDD - 1.4V. The following equation represents the resulting output voltage:
REF AGND SHOWN FOR ALL 1s ON DAC
N Gain V VOUT = REF 16384
where N is the numeric value of the DAC's binary input code (0 to 16383), VREF is the reference voltage, and Gain is the externally set voltage gain. The maximum output voltage is VDD. The reference pin has a minimum impedance of 18k and is code dependent.
Figure 1. Simplified DAC Circuit Diagram
Power-Down Lockout Power-down lockout disables the software/hardware shutdown mode. A high-to-low transition on PDL brings the device out of shutdown, returning the output to its previous state. Shutdown Pulling SHDN high while PDL is high places the MAX5171/MAX5173 in shutdown mode. Pulling SHDN low does not return the device to normal operation. A high-to-low transition on PDL or an appropriate command from the serial data line is required to exit shutdown (see Table 1 for commands).
Output Amplifier
The MAX5171/MAX5173's DAC output is internally buffered by a precision amplifier with a typical slew rate of 0.6V/s. Access to the output amplifier's inverting input provides flexibility in output gain setting and signal conditioning (see Applications Information). The output amplifier settles to 0.5LSB from a full-scale transition within 12s, when loaded with 5k in parallel with 100pF. Loads less than 2k degrade performance.
Serial Interface
The MAX5171/MAX5173 3-wire serial interface is compatible with SPI/QSPI (Figure 2) and MICROWIRE (Figure 3) interface standards. The 16-bit serial input word consists of two control bits and 14 bits of data (MSB to LSB). The control bits determine the MAX5171/MAX5173's response as outlined in Table 1. The MAX5171/ MAX5173's digital inputs are double buffered, which allows any of the following: * Loading the input register without updating the DAC register. * Updating the DAC register from the input register. * Updating the input and DAC registers simultaneously.
Shutdown Mode
The MAX5171/MAX5173 feature a software- and hardware-programmable shutdown mode that reduces the typical supply current to 1A. Enter shutdown by writing the appropriate input-control word as shown in Table 1, or by using the hardware shutdown. In shutdown mode, the reference input and amplifier output become highimpedance, and the serial interface remains active. Data in the input register is saved, allowing the MAX5171/MAX5173 to recall the prior output state when returning to normal operation. To exit shutdown, reload the DAC register from the shift register by simultaneously loading the input and DAC registers or by toggling PDL. When returning from shutdown, wait 40s for the output to settle.
10
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Low-Power, Serial, 14-Bit DACs with Force/Sense Voltage Output
+5V
SS DIN MOSI
The MAX5171/MAX5173 accepts one 16-bit packet or two 8-bit packets sent while CS remains low. The MAX5171/MAX5173 allow the following to be configured: * Clock edge on which serial data output (DOUT) is clocked. * State of the user-programmable logic output. * Configuration of the reset state. Specific commands for setting these are shown in Table 1. The general timing diagram in Figure 4 illustrates how the MAX5171/MAX5173 acquire data. CS must go low at least tCSS before the rising edge of the serial clock (SCLK). With CS low, data is clocked into the register on the rising edge of SCLK. The maximum serial clock frequency guaranteed for proper operation is 10MHz for the MAX5171 and 6MHz for the MAX5173. See Figure 5 for a detailed timing diagram of the serial interface.
MAX5171/MAX5173
MAX5171 MAX5173
SCLK
SCK
SPI/QSPI PORT
CS
I/O
CPOL = 0, CPHA = 0
Figure 2. Connections for SPI/QSPI
Serial Data Output (DOUT)
SCLK SK
MAX5171 MAX5173
DIN
SO
MICROWIRE PORT
CS
I/O
The serial-data output, DOUT, is the internal shift register's output; it allows for daisy-chaining of multiple devices as well as data readback (see Applications Information). By default upon start-up, data shifts out of DOUT on the serial clock's rising edge (Mode 0) and provides a lag of 16 clock cycles, thus maintaining SPI, QSPI, and MICROWIRE compatibility. However, if the device is programmed for Mode 1, then the output data lags DIN by 16.5 clock cycles and is clocked out on the serial clock's rising edge. During shutdown, DOUT retains its last digital state prior to shutdown.
Figure 3. Connections for MICROWIRE
User-Programmable Logic Output (UPO)
The UPO allows control of an external device through the serial interface, thereby reducing the number of
Table 1. Serial-Interface Programming Commands
16-BIT SERIAL WORD C1 0 0 1 1 1 1 1 1 1 C0 0 1 0 1 1 1 1 1 1 D13..................D0 14-bit DAC data 14-bit DAC data x x x xxx xxxx xxxx 0 0 x xxx xxxx xxxx 0 1 x xxx xxxx xxxx 1 0 0 xxx xxxx xxxx 1 0 1 xxx xxxx xxxx 1 1 0 xxx xxxx xxxx 1 1 1 xxx xxxx xxxx FUNCTION Load input register; DAC registers are unchanged. Load input register; DAC registers are updated (start up DAC with new data). Update DAC register from input register (start up DAC with data previously stored in the input registers). No operation (NOP). Shut down DAC (provided PDL = 1). UPO goes low (default). UPO goes high. Mode 1, DOUT clocked out on SCLK's rising edge. Mode 0, DOUT clocked out on SCLK's falling edge (default).
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Low-Power, Serial, 14-Bit DACs with Force/Sense Voltage Output MAX5171/MAX5173
CS COMMAND EXECUTED 1 DIN C2 C1 C0 D9 D8 D7 D6 8 D5 D4 9 D3 D2 D1 D0 S2 S1 16 S0
SCLK
Figure 4. Serial-Interface Timing Diagram
tCSW CS tCSO SCLK tCH tCP DIN tDS DOUT tD01 tD02 tDH tCL tCSS tCSH tCS1
Figure 5. Detailed Serial-Interface Timing Diagram
microcontroller I/O pins required. During power-down, this output will retain its digital state prior to shutdown. When CLR is pulled low, UPO will reset to its programmed default state. See Table 1 for specific commands to control the UPO.
___________Applications Information
Unipolar Output
Figure 6 shows the MAX5171/MAX5173 configured for unipolar, rail-to-rail operation with a gain of +2V/V. Table 2 lists the codes for unipolar output voltages. The output voltage is limited to VDD .
Reset (RS) and Clear (CLR)
The MAX5171/MAX5173 offers a clear pin which resets the output voltage. If RST = DGND, then CLR resets the output voltage to the minimum voltage (0 if no offset is introduced). If RST = VDD, then CLR resets the output voltage to midscale. In either case, CLR resets UPO to its programmed default state.
Bipolar Output
Figure 7 shows the MAX5171/MAX5173 configured for bipolar output operation. The output voltage is given by the following equation (FB = OUT): 2 N VOUT = VREF - 1 16384 where N represents the numeric value of the DAC's binary input code and VREF is the voltage of the external reference. Table 3 shows digital codes and the corresponding output voltage for Figure 7's circuit.
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Low-Power, Serial, 14-Bit DACs with Force/Sense Voltage Output MAX5171/MAX5173
10k 10k
+5V/+3.3V REF VDD FB 10k 10k DAC OUT
REF +5V/+3.3V VDD FB VOUT DAC OUT V-
V+
MAX5171 MAX5173
GND
MAX5171 MAX5173
GND
Figure 6. Unipolar Output Circuit (Rail-to-Rail)
Figure 7. Bipolar Output Circuit
Table 2. Unipolar Code Table (Circuit of Figure 6)
DAC CONTENTS MSB LSB 11 1111 1111 1111 10 0000 0000 0001 10 0000 0000 0000 01 1111 1111 1111 00 0000 0000 0001 00 0000 0000 0000 ANALOG OUTPUT 2 * VREF (16383/16384) 2 * VREF (8193/16384) 2 * VREF (8192/16384) 2 * VREF (8191/16384) 2 * VREF (1/16384) 0
Table 3. Bipolar Code Table (Circuit of Figure 7)
DAC CONTENTS MSB LSB 11 1111 1111 1111 10 0000 0000 0001 10 0000 0000 0000 01 1111 1111 1111 00 0000 0000 0001 00 0000 0000 0000 ANALOG OUTPUT +VREF [(2 * 16383/16384) - 1] +VREF [(2 * 8193/16384) - 1] +VREF [(2 * 8192/16384) - 1] +VREF [(2 * 8191/16384) - 1] +VREF [(2 * 1/16384) - 1] -VREF
Daisy-Chaining Devices
The serial data output pin (DOUT) allows multiple MAX5171/MAX5173s to be daisy-chained together, as shown in Figure 8. The advantage of this is that only two lines are needed to control all of the DACs on the line. The disadvantage is that it takes n commands to program the DACs. Figure 9 shows several MAX5171/ MAX5173s sharing one common DIN signal line. In this configuration, the data bus is common to all devices. However, this configuration uses more I/O lines because each device requires a dedicated CS line. The benefit is that only one command is needed to program any DAC.
Digitally Programmable Current Source
The circuit of Figure 11 places an NPN transistor (2N3904 or similar) within the op amp feedback loop to implement a digitally programmable, unidirectional current source. The output current is calculated with the following equation: V N IOUT = REF R 16384 where N is the numeric value of the DAC's binary input code and R is the sense resistor shown in Figure 11.
Using an AC Reference
The MAX5171/MAX5173 accepts reference voltages with AC components as long as the reference voltage remains between 0 and VDD - 1.4V. Figure 10 shows a technique for applying a sine-wave signal to the REF. The reference voltage must remain above AGND.
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13
Low-Power, Serial, 14-Bit DACs with Force/Sense Voltage Output MAX5171/MAX5173
Power-Supply and Layout Considerations
Wire-wrap boards are not recommended. For optimum system performance, use PC boards with separate analog and digital ground planes. Connect the two ground planes together at the low-impedance powersupply source. Connect the DGND and AGND pins together at the IC. The best ground connection is achieved by connecting the DAC's DGND and AGND pins together and connecting that point to the system analog ground plane. If the DAC's DGND is connected to the system digital ground, digital noise may get through to the DAC's analog portion. Bypass the power supply with a 4.7F capacitor in parallel with a 0.1F capacitor to AGND. Minimize the capacitor lead lengths to reduce inductance. If noise becomes an issue, use shielding and/or ferrite beads to increase isolation. To maintain INL and DNL performance, as well as gain drift, it is extremely important to provide the lowest possible reference output impedance at the DAC reference input pin. INL degrades if the series resistance on the REF pin exceeds 0.1. The same consideration must be made for the AGND pin.
SCLK
SCLK
SCLK
MAX5171 MAX5173
DIN CS DOUT DIN CS
MAX5171 MAX5173
DOUT DIN CS
MAX5171 MAX5173
DOUT
TO OTHER SERIAL DEVICES
Figure 8. Daisy-Chaining MAX5171/MAX5173 Devices
DIN SCLK CS1 CS2 CS3 TO OTHER SERIAL DEVICES
CS
CS
CS
MAX5171 MAX5173
SCLK DIN SCLK DIN
MAX5171 MAX5173
SCLK DIN
MAX5171 MAX5173
Figure 9. Multiple MAX5171/MAX5173s Sharing Common DIN and SCLK Lines
14 ______________________________________________________________________________________
Low-Power, Serial, 14-Bit DACs with Force/Sense Voltage Output MAX5171/MAX5173
+5V/ +3V +5V/+3V R1 AC REFERENCE INPUT
MAX495
+5V/+3.3V REF VDD VL DAC OS
MAX5171 MAX5173
OUT
IOUT 2N3904
500mVp-p
R2
REF
VDD
DAC OUT GND
FB
R
MAX5171 MAX5173
GND
Figure 10. AC Reference Input Circuit
Figure 11. Digitally Programmable Current Source
Functional Diagram
CS DIN SCLK VDD AGND DGND
PDL SHDN
SERIAL CONTROL
16-BIT SHIFT REGISTER
DOUT LOGIC OUTPUT UPO
RS CLR
DECODE CONTROL
FB
MAX5171 MAX5173
INPUT REGISTER
DAC REGISTER
DAC
OUT
REF
Chip Information
TRANSISTOR COUNT: 3457
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15
Low-Power, Serial, 14-Bit DACs with Force/Sense Voltage Output MAX5171/MAX5173
Package Information
QSOP.EPS
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
16 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 1999 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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